key: cord-0056815-6ndw46y2 authors: Gong, Nanbo title: Multi level cell (MLC) in 3D crosspoint phase change memory array date: 2021-03-01 journal: Sci DOI: 10.1007/s11432-021-3184-5 sha: 8ac76be5cd08a7cf71833c460e09a56434f10a68 doc_id: 56815 cord_uid: 6ndw46y2 nan The success of memory technology is of vital importance in order to handle emerging mass amount of data in our daily lives. Let us take one example here: The IBM summit is the supercomputer released in 2018 and it plays an important role to help researchers run large numbers of calculations and better understand COVID-19 1) . To enable such powerful computing capability, the IBM summit includes 250 petabytes storage capacity 2) . To make a fair comparison, this is larger than the total number of all the ants we can find on the earth (on the order of 10 16 -10 17 ) 3) . Unfortunately, the performance of the memory chips still has so much room for improvement because of the big performance gap between the dynamic-random-access-memory (DRAM) and the flash memory. DRAM is volatile and the stored charge in a DRAM cell will gradually leak out, requiring periodic refresh operation that causes significant power consumption. In contrast, flash memories are suffering from slow access speed and limited endurance characteristics. As such, the performance of chips would be further improved by including the storage class memory (SCM) into the state-of-the-art memory hierarchy and bridge the performance gap between DRAM and Flash memory [1] . Among different non-volatile memory candidates [2, 3] , the phase change memory (PCM) technology is considered as one of the most suitable SCM options, which offers reasonable switching speed (between the ones from DRAM and Flash memory), non-volatility, robust endurance and high density [1] . MLC in 1T1R PCM array. To further enhance the density of a PCM array, the multi level cell (MLC) approach is desired. Based on resistance in the phase change material, a PCM cell can be set into a low resistance crystalline state, a high resistance amorphous state, or intermediates between them. With appropriate write-read-verification process, it has been demonstrated that PCM is capable to be programmed into 4 levels (2 bits) with the help of transistors to precisely control the programming current that is applied to the PCM device [4] . Because of the demonstrated 2 bits per cell capability, the whole PCM array is capable to double its density. Although such MLC operation is proved to be possible in a 1 transistor 1 resistor (1T1R) array, the use of transistors limit the density of the array, because transistors are difficult to scale down while providing sufficient enough programming current to write the PCM devices. Another consideration is the balance between using write-readverification and the latency to operate the PCM arrays. As PCM is aiming for the SCM application, it would be necessary to consider the latency penalty if write-read-verification must be implemented to achieve the MLC operation. That said, the most ideal situation is to use a no-transistor PCM array and successfully obtain MLC results without the need of applying write-read-verification procedures. OTS-PCM crosspoint array. With respect to the notransistor PCM array, a PCM cell shows high density potential and it is compatible to be integrated with the two terminal selector devices. It has been shown the memory cell with PCM/barrier/selector can be built using selfaligned process and provides the smallest memory cell footprint (4F 2 ) in a 2D-array [5] . Among several selector options, the ovonic threshold switch (OTS) not only shows sufficient switching time and on-off ratio, but also shows unique potential because of its compatibility to PCM. The back-end-of-line (BEOL) compatible process to fabricate the PCM/barrier/OTS cells makes it a promising technology that is suitable for a 3D crosspoint array, providing a higher density solution than the 2D-array [6] [7] [8] . Recently, significant progresses have been reported for the 3D crosspoint technology, showing great potential for a OTS-PCM array to meet all the SCM application requirements at the same time [9, 10] . grammed while the selected cell encounters sufficient programming current and is successfully set or reset accordingly. To write and read the selected cells without turning on unselected cells, the so-called half-selected operating schemes are the most commonly used. Under this scheme, the selected cell could be successfully set and reset by the program voltage, in the meanwhile, the unselected cells stay in "off " state because they face maximum half of the program voltage that is below the threshold switching condition of the OTS-PCM cell [11] . The half-selected scheme requires strict program voltage operating ranges in order to make sure both selected and unselected cells would work as expected, and the limited window of such operating voltage range provides difficulties to obtain sizeable memory window to distinguish different levels of the PCM resistance in a crosspoint array. In addition, PCM is known to suffer from resistance and threshold voltage (Vt) drift [8] . After resetting the PCM cell, resistance of the PCM gradually moves towards to a higher resistance level, so it is with the threshold voltage. This may not be an obvious issue for a binary bit device application, but it is detrimental for the MLC application because the whole MLC operation is no longer valid anymore if any level fails to be distinguished from the others. In the meanwhile, the OTS selector also shows threshold switching, and the root cause of the selector Vt drift still requires more understanding. As a result, it would be important to understand what is the characteristics of Vt drift in an OTS-PCM cell, and the Vt drift in the cell is a critical issue to overcome in order to make sure an MLC operation would be functional in the OTS-PCM crosspoint array. A no-verification MLC operation in the OTS-PCM crosspoint array. Recent studies have reported the significant progress on the MLC operations for an OTS-PCM crosspoint array, and an open-loop programming MLC operation in an OTS-PCM crosspoint array has been demonstrated thanks to improved characteristics of the OTS-PCM cells within a 1Mbit array, such as tight Vt distributions and sizeable memory windows [12] . The so called open loop programming avoids the iterative read-verify-rewrite procedure and only applies one write pulse that is desired to program the cell to the target value whenever the cell is written (i.e., without the read and rewrite procedure). The success of this no-verification operation offers a great opportunity to fully utilize the fast write speed characteristics of the PCM devices, making it suitable for the SCM applications. In addition, the critical Vt drift is also comprehensively studied, and it shows that Vt drift is not sensitive to resistance level of the PCM but sensitive to the programming methods that are used to write the PCM into multi-level cell states. It suggests the open-loop programming MLC operation is possible to achieve by adopting suitable programming methods, and Vt drift is able to be modulated accordingly. To further reduce the impact from Vt drift and improve the MLC performance in the OTS-PCM array, material innovation would serve as a silver bullet. It has been shown that with Si incorporated into AsSeGe system, the OTS selector Vt drift is capable to be mitigated significantly [13] . Conclusion. Improving performance of future computing systems requires developing PCM technology to serve as an SCM candidate and bridge the performance gap between DRAM and Flash memory. PCM is capable to be programmed into multi-level and also can be integrated with an OTS selector into a high density crosspoint array without transistors. It is ideal to obtain no-verification-rewirte open-loop programming MLC operation in a no-transistor OTS-PCM crosspoint array, and the challenges to overcome includes sizeable memory window and Vt drift. Recent studies have demonstrated the possibility to obtain such ideal operation in OTS-PCM crosspoint array, with the help of tight distribution of memory window and adopting optimized programming methods that would mitigate Vt drift. It is promising to observe MLC is a feasible approach to further improve future computing system performance, and material innovation would be an important approach to further enhance the MLC performance in the OTS-PCM crosspoint array down the road. Novel lithography-independent pore phase change memory Retention and endurance of FeFET memory cells Signal and noise extraction from analog memory elements for neuromorphic computing A novel selfconverging write scheme for 2-bits/cell phase change memory for storage class memory (SCM) application Programmable Phase Change Memory. US Patent, 6 579 760 Ultra-high endurance and low IOFF selector based on AsSeGe chalcogenides for wide memory window 3D stackable crosspoint memory High endurance self-heating OTS-PCM pillar cell for 3D stackable memory 3D cross-point phase-change memory for storage-class memory A stackable cross point phase change memory High-performance, costeffective 2z nm two-deck cross-point memory integrated by self-align scheme for 128 Gb SCM Comprehensive scaling study on 3D cross-point PCM toward 1Z nm Node for SCM Applications A no-verification multi-level-cell (MLC) operation in cross-point OTS-PCM: IBM/macronix phase change memory joint project Si incorporation into AsSeGe chalcogenides for high thermal stability, high endurance and extremely low vth drift 3D stackable cross-point memory: IBM/macronix PCRAM joint project Acknowledgements The author would like to thank Dr. W-C Chien and other colleagues from IBM T.J. Waston Research Center and Macronix International, Emerging Central Lab, for their feedback to this work, and also thank Dr. M. BrightSky, Dr. H -L Lung for management support from IBM-Macronix phase change memory joint project. The author would especially thank Dr. V. Narayanan for management support.