Microscopic properties of semiconducting nanostructures are very sensitive to perturbations at the semiconductor/environment surface. Charge transport prop- erties in semiconducting nanostructures can dramatically change by the interac- tion mediated by the dielectric environment surrounding them. In this work, the effect of the dielectric mismatch between a semiconductor and its dielectric envi- ronment on charge transport in 1D quantum wires and 2D nanoscale membranes is investigated. It is shown that the image charges formed at the semiconduc- tor/environment interfaces alter the Coulomb potential and the electron-electron interaction inside the low dimensional structures. It is predicted that by coat- ing nanostructures with high-Ì_å¼ dielectrics, carrier mobility in quasi-1D nanowires and quasi-2D nanomembranes can be enhanced by an order of magnitude if the charge transport is impurity-limited. For perfect 2D crystals such as graphene, this mobility enhancement is only possible at low temperatures, whereas at room temperature polar phonon vibrations originating from the dielectric environment wash out the advantages of using high-Ì_å¼ dielectrics. The work presented here will help to identify the optimum gate dielectric for designing high-mobility, high-speed nanoscale transistors.