Moore's law, which aims to double the number of transistors in the same area every 18 months, has been in full swing over the last 60 years. Almost every high-performance chip company considered moving to the next available technology node as a primary way to maximize value, however, with Moore's law slowing down, it is necessary to start looking at different strategies that are more closely aligned with the individual needs of each application. Without the expected device performance boost every 18 months, industries have started looking closely at each step in the production chain providing many opportunities to improve performance outside of simply reducing the scale of the transistors. Our novel work explores and optimizes oxide-based emerging devices for logic, memory, neuromorphic computing and high frequency applications. We performed electrical characterization of several devices and developed high-fidelity, compact circuit-level models. These models bridge the different levels of the supply chain allowing us to exploit the performance of these novel devices for specific applications. For instance, for logic applications we modeled, built, and tested doped-Hafnuim Dioxide based ferroelectric field effect transistors (FeFET). We then utilized these experimentally calibrated compact models to explore the phenomenon of Negative Capacitance (NC). This phenomenon can be harnessed to provide a boost in logic transistor performance. We also proposed and experimentally demonstrated the utilization of an amorphous semiconductor oxide channel transistor using a Tungsten-doped Indium Oxide transistor. This transistor provides ultra-low leakage and is back-end-of-line (BEOL) compatible. Using these devices, we modeled, built, and tested a BEOL compatible embedded DRAM (eDRAM) with ultra-long refresh time.