Tunnel field-effect transistors (TFETs) are under intense investigation for low-power applications because of their potential for low subthreshold swing (SS) and low off-state leakage (IOFF). To achieve high on current (ION) and steep SS in TFETs, TFETs based on III-V semiconductors with small effective mass and favorable band alignment have been investigated by several groups. The focus of this dissertation is on the design, fabrication and characterization of such TFETs. The interface between InGaAs and high k dielectrics by atomic layer deposition (ALD) was first studied, which is critical for TFETs. A novel TFET geometry with tunneling direction normal to the gate was then designed; and the early generations of TFETs were fabricated on an InGaAs/InP heterojunction and an InAs/AlGaSb heterojunction, showing promising results: ION/IOFF ~ 106, ION > 30 μA/μm at VDS = VGS = 1 V and SSMIN = 93 mV/dec. To further improve TFETs device performance, another novel gate-recess process was successfully developed featuring a completely self-aligned device topology and excellent ohmic contacts (150 Ω'¢μm). Another generation of the TFETs was demonstrated using an InAs/(Al)GaSb tunnel junction with a (near) broken band alignment. The InAs/GaSb TFETs with the favorable broken gap alignment fabricated using the gate-recess process have shown a record high ION of 180 μA/μm at VDS = VGS = 0.5 V with an ION/IOFF ratio of 6x103. The effects of effective oxide thickness (EOT) scaling, ALD oxide and plasma-enhanced chemical vapor deposition (PECVD) SiNx passivation, forming gas annealing (FGA) and temperature dependence on the TFET performance were also investigated. Finally, various mechanisms limiting the TFETs performance such as on-current, off-current and SS have been examined.