Quilt Packaging (QP) is a novel, high-speed, direct interchip interconnection technology invented and developed at The University of Notre Dame. Quilt Packaging uses conducting structures, called 'nodules,' that protrude from the thin, vertical faces of a chip, connecting to matching structures on an adjacent chip, forming a high-performance and dense system-in-package. Groups of chips are tiled much like cloth pieces in a patchwork quilt, so a group of tiled, or 'quilted,' chips are called 'quilts' or 'metachips.' As an emerging technology, Quilt Packaging has novel failure modes that require investigation. In this work, a reliable structure for quilted chips is proposed and demonstrated. Simulation models are developed to study the failure modes of QP. Simulations based on material properties and static, uniform temperature provide guidelines for the size of interconnects and materials to use for a reliable QP structure. Additionally, simulation results are used to explore the most vulnerable regions of the structure, and are verified by experiments. Some ways of reducing stress at the critical areas is addressed. The number of failure cycles for the QP nodules is estimated using simulation results and a fatigue failure model. Test structures are fabricated. We use both thermal cycling and thermal shock tests to examine the failure modes of individual QP chips (i.e., unquilted) as well as two-chip metachips, focusing on reliability issues for various shapes. To explore the test results, both noninvasive and invasive methods are used. The test results are consistent with simulation results; viable operating temperature ranges are also identified.