As we continue to approach the physical scaling limits of CMOS transistors, microprocessors no longer achieve exponential performance gains per each technology node generation. This performance attenuation is attributed to the diminishing rate of supply voltage scaling and the increasing sub-threshold leakage current. These have resulted in a growing---as opposed to constant---power density, which has given birth to the dark silicon (DS) problem. To overcome the limitations of CMOS, solutions are sought from the device to the architectural level. Beyond-CMOS devices represent a class of candidate technologies with the potential to succeed traditional CMOS. As new electronic (charge based) and spintronic (spin based) devices are continually developed and refined, benchmarking against CMOS becomes a necessary endeavor. In this context, my work has involved the design and evaluation of circuits and architectures comprised of emerging electronic and spintronic devices. To this end, I have constructed analytical benchmarking models to evaluate CMOS and beyond-CMOS technologies. For electronic beyond-CMOS technologies, I have designed an analytical benchmarking model that considers device-, processor-, and application-level parameters, and projects the performance and percentage of on-chip dark silicon. Using empirical CMOS processor data, I validated my model's projections by demonstrating a close relationship between projected and empirical CMOS data for three different technology nodes (i.e., 32 nm, 22 nm, and 15 nm).Spintronic beyond-CMOS technologies are of particular interest due to their high integration density, low device count, radiation hardness, and non-volatility when compared to CMOS. For spintronic devices, my work has involved (i) the systematic design of functional 3D Nanomagnetic Logic (NML) layouts (i.e., logic gates), (ii) exploring the benefits of NML-based Stochastic Computing (SC), and (iii) the design of an analytical benchmarking model that is based on a processor-level drop-in approach to project the energy per operation of various spintronic technologies.NML uses bistable magnets to store, process, and move binary information through magnetic field-coupled interactions. Compared to CMOS, NML has several advantages such as non-volatility, lower power consumption, and radiation hardness. 3D NML layouts provide additional benefits such as simplified signal routing and greater integration density. The current process of designing 3D NML layouts is little more than a trial-and-error-based approach, which is infeasible for larger, more complex designs. To address this design limitation, I developed a systematic approach that leverages a machine learning-inspired prediction methodology to enable faster design of functional 3D NML layouts.The systematic design approach facilitated the study of more complex computational paradigms such as SC. SC offers low-cost implementations of arithmetic operations and high degrees of error tolerance. Given that spintronic devices such as NML are more prone to error than electronic devices, the marriage of SC and spin-based devices has the potential to produce information processing systems that are robust, low energy and non-volatile. I introduced and evaluated new NML layouts that exploited unique features of the technology to efficiently realize hardware components required for SC.Quantifying the impact of spintronic non-volatile (NV) technologies at the architecture and application levels introduces a unique challenge as the granularity of technology integration can vary significantly (i.e., from heterogeneous architectures with NV cache and CMOS-based logic, to completely NV architectures). To this end, I designed an analytical model to explore three classes of NV processors (NVPs) and defined metrics for quantifying their respective energy savings. As case studies, I evaluated the impact of NV technologies for both an energy harvesting non-pipelined processor and a general purpose processor executing scientific applications under varying degrees of parallelism.