id	sid	tid	token	lemma	pos
tb09j388f4p	1	1	chip	chip	NOUN
tb09j388f4p	1	2	multiprocessors	multiprocessor	NOUN
tb09j388f4p	1	3	are	be	AUX
tb09j388f4p	1	4	one	one	NUM
tb09j388f4p	1	5	of	of	ADP
tb09j388f4p	1	6	several	several	ADJ
tb09j388f4p	1	7	emerging	emerge	VERB
tb09j388f4p	1	8	architectures	architecture	NOUN
tb09j388f4p	1	9	that	that	PRON
tb09j388f4p	1	10	address	address	VERB
tb09j388f4p	1	11	the	the	DET
tb09j388f4p	1	12	growing	grow	VERB
tb09j388f4p	1	13	processor	processor	NOUN
tb09j388f4p	1	14	memory	memory	NOUN
tb09j388f4p	1	15	performance	performance	NOUN
tb09j388f4p	1	16	gap	gap	NOUN
tb09j388f4p	1	17	.	.	PUNCT
tb09j388f4p	2	1	at	at	ADP
tb09j388f4p	2	2	the	the	DET
tb09j388f4p	2	3	same	same	ADJ
tb09j388f4p	2	4	time	time	NOUN
tb09j388f4p	2	5	,	,	PUNCT
tb09j388f4p	2	6	advances	advance	NOUN
tb09j388f4p	2	7	in	in	ADP
tb09j388f4p	2	8	chip	chip	NOUN
tb09j388f4p	2	9	manufacturing	manufacturing	NOUN
tb09j388f4p	2	10	enable	enable	VERB
tb09j388f4p	2	11	the	the	DET
tb09j388f4p	2	12	integration	integration	NOUN
tb09j388f4p	2	13	of	of	ADP
tb09j388f4p	2	14	processing	processing	NOUN
tb09j388f4p	2	15	logic	logic	NOUN
tb09j388f4p	2	16	and	and	CCONJ
tb09j388f4p	2	17	dense	dense	ADJ
tb09j388f4p	2	18	dram	dram	NOUN
tb09j388f4p	2	19	on	on	ADP
tb09j388f4p	2	20	the	the	DET
tb09j388f4p	2	21	same	same	ADJ
tb09j388f4p	2	22	die	die	NOUN
tb09j388f4p	2	23	.	.	PUNCT
tb09j388f4p	3	1	this	this	DET
tb09j388f4p	3	2	thesis	thesis	NOUN
tb09j388f4p	3	3	analyzes	analyze	VERB
tb09j388f4p	3	4	the	the	DET
tb09j388f4p	3	5	use	use	NOUN
tb09j388f4p	3	6	of	of	ADP
tb09j388f4p	3	7	such	such	ADJ
tb09j388f4p	3	8	merged	merge	VERB
tb09j388f4p	3	9	dram	dram	NOUN
tb09j388f4p	3	10	as	as	ADP
tb09j388f4p	3	11	a	a	DET
tb09j388f4p	3	12	shared	shared	ADJ
tb09j388f4p	3	13	cache	cache	NOUN
tb09j388f4p	3	14	for	for	ADP
tb09j388f4p	3	15	a	a	DET
tb09j388f4p	3	16	large	large	ADJ
tb09j388f4p	3	17	-	-	PUNCT
tb09j388f4p	3	18	scale	scale	NOUN
tb09j388f4p	3	19	chip	chip	NOUN
tb09j388f4p	3	20	multiprocessor	multiprocessor	NOUN
tb09j388f4p	3	21	.	.	PUNCT
tb09j388f4p	4	1	simulation	simulation	NOUN
tb09j388f4p	4	2	results	result	NOUN
tb09j388f4p	4	3	reveal	reveal	VERB
tb09j388f4p	4	4	that	that	SCONJ
tb09j388f4p	4	5	maximizing	maximize	VERB
tb09j388f4p	4	6	concurrency	concurrency	NOUN
tb09j388f4p	4	7	in	in	ADP
tb09j388f4p	4	8	the	the	DET
tb09j388f4p	4	9	cache	cache	NOUN
tb09j388f4p	4	10	is	be	AUX
tb09j388f4p	4	11	of	of	ADP
tb09j388f4p	4	12	paramount	paramount	ADJ
tb09j388f4p	4	13	importance	importance	NOUN
tb09j388f4p	4	14	,	,	PUNCT
tb09j388f4p	4	15	greater	great	ADJ
tb09j388f4p	4	16	even	even	ADV
tb09j388f4p	4	17	than	than	SCONJ
tb09j388f4p	4	18	cache	cache	PROPN
tb09j388f4p	4	19	hit	hit	VERB
tb09j388f4p	4	20	rate	rate	NOUN
tb09j388f4p	4	21	.	.	PUNCT
tb09j388f4p	5	1	concurrency	concurrency	NOUN
tb09j388f4p	5	2	is	be	AUX
tb09j388f4p	5	3	achieved	achieve	VERB
tb09j388f4p	5	4	through	through	ADP
tb09j388f4p	5	5	ports	port	NOUN
tb09j388f4p	5	6	gained	gain	VERB
tb09j388f4p	5	7	from	from	ADP
tb09j388f4p	5	8	creating	create	VERB
tb09j388f4p	5	9	a	a	DET
tb09j388f4p	5	10	multi	multi	ADJ
tb09j388f4p	5	11	-	-	ADJ
tb09j388f4p	5	12	banked	banked	ADJ
tb09j388f4p	5	13	cache	cache	NOUN
tb09j388f4p	5	14	,	,	PUNCT
tb09j388f4p	5	15	and	and	CCONJ
tb09j388f4p	5	16	multiple	multiple	ADJ
tb09j388f4p	5	17	paths	path	NOUN
tb09j388f4p	5	18	to	to	ADP
tb09j388f4p	5	19	main	main	ADJ
tb09j388f4p	5	20	memory	memory	NOUN
tb09j388f4p	5	21	.	.	PUNCT
tb09j388f4p	6	1	results	result	NOUN
tb09j388f4p	6	2	demonstrate	demonstrate	VERB
tb09j388f4p	6	3	that	that	SCONJ
tb09j388f4p	6	4	maximizing	maximize	VERB
tb09j388f4p	6	5	the	the	DET
tb09j388f4p	6	6	number	number	NOUN
tb09j388f4p	6	7	of	of	ADP
tb09j388f4p	6	8	cache	cache	NOUN
tb09j388f4p	6	9	banks	bank	NOUN
tb09j388f4p	6	10	is	be	AUX
tb09j388f4p	6	11	the	the	DET
tb09j388f4p	6	12	most	most	ADV
tb09j388f4p	6	13	important	important	ADJ
tb09j388f4p	6	14	design	design	NOUN
tb09j388f4p	6	15	goal	goal	NOUN
tb09j388f4p	6	16	,	,	PUNCT
tb09j388f4p	6	17	followed	follow	VERB
tb09j388f4p	6	18	by	by	ADP
tb09j388f4p	6	19	providing	provide	VERB
tb09j388f4p	6	20	adequate	adequate	ADJ
tb09j388f4p	6	21	associativity	associativity	NOUN
tb09j388f4p	6	22	to	to	PART
tb09j388f4p	6	23	minimize	minimize	VERB
tb09j388f4p	6	24	miss	miss	VERB
tb09j388f4p	6	25	rates	rate	NOUN
tb09j388f4p	6	26	.	.	PUNCT
tb09j388f4p	7	1	furthermore	furthermore	ADV
tb09j388f4p	7	2	,	,	PUNCT
tb09j388f4p	7	3	the	the	DET
tb09j388f4p	7	4	optimal	optimal	ADJ
tb09j388f4p	7	5	cache	cache	NOUN
tb09j388f4p	7	6	block	block	NOUN
tb09j388f4p	7	7	size	size	NOUN
tb09j388f4p	7	8	is	be	AUX
tb09j388f4p	7	9	heavily	heavily	ADV
tb09j388f4p	7	10	dependent	dependent	ADJ
tb09j388f4p	7	11	on	on	ADP
tb09j388f4p	7	12	the	the	DET
tb09j388f4p	7	13	workload	workload	NOUN
tb09j388f4p	7	14	.	.	PUNCT
tb09j388f4p	8	1	the	the	DET
tb09j388f4p	8	2	off	off	ADJ
tb09j388f4p	8	3	-	-	PUNCT
tb09j388f4p	8	4	chip	chip	NOUN
tb09j388f4p	8	5	memory	memory	NOUN
tb09j388f4p	8	6	organization	organization	NOUN
tb09j388f4p	8	7	impacts	impact	VERB
tb09j388f4p	8	8	performance	performance	NOUN
tb09j388f4p	8	9	to	to	ADP
tb09j388f4p	8	10	a	a	DET
tb09j388f4p	8	11	lesser	less	ADJ
tb09j388f4p	8	12	degree	degree	NOUN
tb09j388f4p	8	13	,	,	PUNCT
tb09j388f4p	8	14	with	with	ADP
tb09j388f4p	8	15	providing	provide	VERB
tb09j388f4p	8	16	multiple	multiple	ADJ
tb09j388f4p	8	17	paths	path	NOUN
tb09j388f4p	8	18	to	to	ADP
tb09j388f4p	8	19	memory	memory	NOUN
tb09j388f4p	8	20	outperforming	outperform	VERB
tb09j388f4p	8	21	a	a	DET
tb09j388f4p	8	22	wider	wide	ADJ
tb09j388f4p	8	23	memory	memory	NOUN
tb09j388f4p	8	24	bus	bus	NOUN
tb09j388f4p	8	25	.	.	PUNCT