id	author	title	date	pages	extension	mime	words	sentence	flesch	summary	cache	txt
st74cn7372x	Jake P. Leporte	Control and Dataflow in 28 nm CMOS for a FeFET-Based Compute-in-Memory Tensor Algebra Accelerator	2022		.txt	text/plain	173	5	37	This design includes a circuit for per-ADC asynchronous capture and forwarding of CIM outputs, a re-configurable adder tree taking advantage of the naturally ternary FeFET array weights, a memory system which uses banking and shift-registers to interface at high-bandwidth to the CIM array, and an abstracted programming interface suitable for further exploration of accelerator-algorithm co-design. This thesis proposes that a simple custom digital control system and a banked-memory-based dataflow and be effectively combined with a CIM array to exploit the unique architectural advantages offered by CIM.	cache/st74cn7372x.txt	txt/st74cn7372x.txt