id	author	title	date	pages	extension	mime	words	sentence	flesch	summary	cache	txt
sq87br88s59	Shyamkumar Thoziyoor	A comprehensive memory modeling tool for design and analysis of future memory hierarchies	2008		.txt	text/plain	396	18	63	CACTI-D also supports the modeling of main memory DRAM chips. In this study we use CACTI-D to model all components of the memory hierarchy including L1, L2, last level SRAM, LP-DRAM or COMM-DRAM based L3 caches, and main memory DRAM chips.	cache/sq87br88s59.txt	txt/sq87br88s59.txt