id	author	title	date	pages	extension	mime	words	sentence	flesch	summary	cache	txt
hh63st76m6h	Patrick Anthony La Fratta	Optimizing the Internal Microarchitecture and ISA of a Traveling Thread PIM System	2010		.txt	text/plain	208	6	11	To address these challenges, this work employs an iterative design methodology in the optimization of an innovative processor architecture that leverages the above features in the implementation of an advanced, powerful execution model called traveling threads for exploiting parallelism and data locality in tandem at multiple levels of granularity. The design of this Passive/Active Multicore (PAM) architecture and the development of mechanisms for locality-cognizant extraction of traveling threads offer insights into the benefits of utilizing computational migration at a granularity of parallelism between the conventional instruction and thread levels.	cache/hh63st76m6h.txt	txt/hh63st76m6h.txt