id	author	title	date	pages	extension	mime	words	sentence	flesch	summary	cache	txt
73666397v85	Amit Kashyap	Exploration of Chip Level Architecture of a Multithreaded PIM System	2010		.txt	text/plain	122	6	46	In particular, we measure the impact of memory latency and degree of banking, outstanding memory references per thread and the network on-chip (NoC) topology on the execution time of micro- benchmarks. Using this simulation tool, we present a bottom up approach for the evaluation of the architecture on a set of micro-benchmarks.	cache/73666397v85.txt	txt/73666397v85.txt