id	author	title	date	pages	extension	mime	words	sentences	flesch	summary	cache	txt
work_c3hqnyrzanhgtgzgi3odcggfey	Giovanni Beltrame	Triple Modular Redundancy verification via heuristic netlist analysis	2015	17	.pdf	application/pdf	7450	1261	46	Fault injection simulators run a given testbench on the design under test (DUT), its driving logic cone, and perform an exhaustive fault injection campaign. that the FFs bounding the logic cone are injected single bit flips in all possible input Testing all possible configurations for a logic cone means 2nf injections, with nodes of this graph have indexed inputs and are associated to a logic function and a value, Having assumed that each FFs has one input, we can define the driving node for a given FF 2. TMR structure analysis: perform an exhaustive fault injection campaign on all valid To determine a useful set of valid configurations for a logic cone (here represented by a The algorithm takes each FF xi and determines the set of FFs that driving its logic In this work we presented an algorithm to verify TMR implementation for given netlists.	./cache/work_c3hqnyrzanhgtgzgi3odcggfey.pdf	./txt/work_c3hqnyrzanhgtgzgi3odcggfey.txt