id	author	title	date	pages	extension	mime	words	sentences	flesch	summary	cache	txt
work_afsxvcg3kfhxbgf5td2lfziyua	Naga Durga Prasad Avirneni	Managing contamination delay to improve Timing Speculation architectures	2016	27	.pdf	application/pdf	12366	1340	71	Also, we propose an algorithm to efficiently add delay buffers to selected short paths contamination delay of digital circuits up to a given threshold, beyond satisfying hold time increase the contamination delay to 30% of the circuit critical path length and also without investigates the timing constraints of TS framework and 'Increasing Short Path Delays' paths of the circuit in 'Min-arc Algorithm for Increasing Short Path Delays.' Results of our the data by meeting the worst-case propagation delay time of the combinational circuit. the impact of contamination delay on timing speculation framework at circuit level. We introduce Min-arc algorithm for increasing contamination delay of logic circuits up The basic outline of the Min-arc algorithm to increase the short path delay of the circuit threshold, the maximum delay increase affecting a critical path is still within propagation into network graphs as described in 'Min-arc Algorithm for Increasing Short Path Delays'.	./cache/work_afsxvcg3kfhxbgf5td2lfziyua.pdf	./txt/work_afsxvcg3kfhxbgf5td2lfziyua.txt