Stanford MIPS - Wikipedia Stanford MIPS From Wikipedia, the free encyclopedia Jump to navigation Jump to search Not to be confused with MIPS architecture or MIPS-X. This article includes a list of general references, but it remains largely unverified because it lacks sufficient corresponding inline citations. Please help to improve this article by introducing more precise citations. (May 2017) (Learn how and when to remove this template message) MIPS, an acronym for Microprocessor without Interlocked Pipeline Stages, was a research project conducted by John L. Hennessy at Stanford University between 1981 and 1984. MIPS investigated a type of instruction set architecture (ISA) now called Reduced Instruction Set Computer (RISC), its implementation as a microprocessor with very large scale integration (VLSI) semiconductor technology, and the effective exploitation of RISC architectures with optimizing compilers. MIPS, together with the IBM 801 and Berkeley RISC, were the three research projects that pioneered and popularized RISC technology in the mid-1980s. In recognition of the impact MIPS made on computing, Hennessey was awarded the IEEE John von Neumann Medal in 2000 by the IEEE (shared with David A. Patterson), the Eckert–Mauchly Award in 2001 by the Association for Computing Machinery, the Seymour Cray Computer Engineering Award in 2001 by the IEEE Computer Society, and, again with David Patterson, the Turing Award in 2017 by the ACM. The project was initiated in 1981 in response to reports of similar projects at IBM (the 801) and the University of California, Berkeley (the RISC). MIPS was conducted by Hennessy and his graduate students until its conclusion in 1984. Hennessey founded MIPS Computer Systems in the same year to commercialize the technology developed by the project. In 1985, MIPS Computer Systems announced a new ISA, also called MIPS, and its first implementation, the R2000 microprocessor. The commercial MIPS ISA, and its implementations went on to be widely used, appearing in embedded computers, personal computers, workstations, servers, and supercomputers. As of May 2017, the commercial MIPS ISA is owned by Imagination Technologies, and is used mainly in embedded computers. In the late 1980s, a follow-up project called MIPS-X was conducted by Hennessy at Stanford. The MIPS ISA was based on a 32-bit word. It supported 32-bit addressing, and was word-addressed. It was a load/store architecture—all references to memory used load and store instructions that copied data between the main memory and 32 general-purpose registers (GPRs). All other instructions, such as integer arithmetic, operated on the GPRs. It possessed a basic instruction set consisting of instructions for control flow, integer arithmetic, and logical operations. To minimize pipeline stalls, all instructions except for load and store had to be executed in one clock cycle. There were no instructions for integer multiplication or division, or operations for floating-point numbers. The architecture exposed all hazards caused by the five-stage pipeline with delay slots. The compiler scheduled instructions to avoid hazards resulting in incorrect computation whilst simultaneously ensuring that the generated code minimized execution time. MIPS instructions are 16 or 32 bit long. The decision to expose all hazards was motivated by the desire to maximize performance by minimizing critical paths, which interlock circuits lengthened. Instructions were packed into 32-bit instruction words (as MIPS is word-addressed). A 32-bit instruction word could contain two 16-bit operations. These were included to reduce the size of machine code. The MIPS microprocessor was implemented in NMOS logic. References[edit] Tanenbaum, Andrew S. Structured Computer Organization (5 ed.). Stallings, William. Computer Organization and Architecture: Designing for Performance (9 ed.). Tabak, Daniel (1987). RISC Architecture. Research Studies Press. pp. 60–68. v t e MIPS microprocessors MIPS architecture MIPS architecture processors List of MIPS architecture processors General processors MIPS64 compatible Loongson 3 Series LS3A1000/LS3A1000-I(LS3A1000-i) LS3A2000/LS3A1500-I LS3A3000/LS3A3000-I(LS3A3000-i) LS3A4000/LS3A4000-I(LS3A4000-i) LS3B1000 LS3B1500 LS3B2000 LS3B3000 LS3B4000 Application processors MIPS32 compatible Ingenic XBurst JZ4720 Ben NanoNote JZ4730 (Skytone Alpha-400) JZ4740 (Dingoo A320) JZ4750 (Game Gadget) JZ4760 Velocity Micro T103 Cruz Velocity Micro T301 Cruz JZ4770 Ainol Novo7 Paladin NEOGEO-X GCW-Zero JZ4780 MIPS64 compatible Loongson 2 Series LS2H LS2K1000/LS2K2000 Microcontrollers (embedded device) M4K Microchip Technology PIC32MX 4Kc/4KEc ATI/AMD/Broadcom Xilleon MIPS32 compatible Loongson 1 Series LS1A0300 LS1B LS1C300 LS1C101 LS1D LS1G LS1H Networking 4Kc/4KEc Qualcomm Atheros AR2313 AR2318 MediaTek RT2880 Texas Instruments/Infineon/Lantiq AR7 Lantiq AMAZON 5Kc Marvell 88E6318 "Link Street" 24Kc/24KEc Qualcomm Atheros AR7240 AR7161 AR9132 AR9331 MediaTek RT3050 RT3052 RT3350 RT5350 RT6856 MT7620 Lantiq DANUBE VINAX 34Kc Lantiq AR188 VRX288 GRX388 Ikanos Fusiv Vx175/173 Fusiv Vx180 Fusiv Vx185/183 74Kc Qualcomm Atheros AR9344 QCA9558 MediaTek RT3662 RT3883 Broadcom BCM4706 1004Kc MediaTek MT7621 1074Kc Realtek RTL8198C MIPS32 compatible Broadcom various Cavium various Alchemy Semiconductor Alchemy RMI Corporation XLR MIPS64 compatible Broadcom various Cavium Octeon Gaming various PlayStation 1 MIPS R3000A-compatible Nintendo 64 NEC VR4300 PlayStation Portable R4000-based PlayStation 2 Emotion Engine Supercomputer MIPS64 compatible Loongson-based systems LS2F/LS2F1000 LS3A1000 LS3B1000 SiCortex Aerospace MIPS64 compatible Loongson 1 Series LS1E0300/LS1E1000 MIPS32 compatible Loongson 1 Series LS1E04 LS1F04/LS1F0300 LS1J Classic processors MIPS I R2000 R3000 MIPS II R6000 MIPS III R4000 R4400 R4200 R4300i R4600 R4700 MIPS IV R5000 R8000 R10000 R12000 R12000A R14000 R14000A R16000 R16000A R18000 MIPS V H1 "Beast" H2 "Capitan" v t e Reduced instruction set computer (RISC) architectures IBM 801 Berkeley RISC Stanford MIPS Active Analog Devices Blackfin ARC ARM AVR eSi-RISC LatticeMico8 LatticeMico32 MIPS OpenRISC Power ISA Renesas M32R Renesas SuperH Renesas V850 RISC-V Sunway SPARC Unicore Xilinx MicroBlaze Xilinx PicoBlaze Historic Alpha AMD Am29000 Apollo PRISM Atmel AVR32 Clipper CRISP DEC Prism Intel i860 Intel i960 Meta MIPS-X Motorola 88000 Motorola M·CORE PA-RISC ROMP POWER PowerPC Retrieved from "https://en.wikipedia.org/w/index.php?title=Stanford_MIPS&oldid=968133094" Categories: MIPS architecture Instruction set architectures Microprocessors American inventions Stanford University Hidden categories: Articles lacking in-text citations from May 2017 All articles lacking in-text citations Navigation menu Personal tools Not logged in Talk Contributions Create account Log in Namespaces Article Talk Variants Views Read Edit View history More Search Navigation Main page Contents Current events Random article About Wikipedia Contact us Donate Contribute Help Learn to edit Community portal Recent changes Upload file Tools What links here Related changes Upload file Special pages Permanent link Page information Cite this page Wikidata item Print/export Download as PDF Printable version Languages Español Edit links This page was last edited on 17 July 2020, at 12:44 (UTC). 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